NXP Semiconductors /MIMXRT1052 /SystemControl /STIR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as STIR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INTID

Description

Instruction cache invalidate all to Point of Unification (PoU)

Fields

INTID

Indicates the interrupt to be triggered

Links

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